Strees-reduced layer system for use in storage capacitors

ABSTRACT

The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This is a division of U.S. application Ser. No. 10/131,358, filedApr. 24, 2002.

BACKGROUND OF THE INVENTION FIELD OF THE INVENTION

[0002] The present invention relates to a stress-reduced layer systemwith at least one polycrystalline or single-crystal semiconductor layerand at least one microcrystalline or amorphous conducting or insulatinglayer.

[0003] Layer systems of this type may, for example, comprisesilicon-dielectric or silicon-metal or dielectric-metal stacks. Stacksof this type are usually produced by, for example, applying a dielectricor metal layer to a silicon substrate or a semiconductor or dielectriclayer, typically using a CVD process.

[0004] In layer systems of this type without stress reduction, theproblem usually occurs that, on account of the different latticeconstants and the different coefficients of thermal expansion of thematerials both at the interface and in the bulk, considerable mechanicalstresses are generated. These stresses must not become too great, sincein the event of a tensile stress the layer which is applied becomesdetached from the other layer, while in the event of a compressivestress defects are produced in the material located below the appliedlayer.

[0005] In general, a distinction is drawn between bulk stress andinterfacial stress. Bulk stress is produced by the lattice stress whichis caused during doping when the doping atoms are incorporated into thecrystal lattice on account of the different atomic radii of doping atomsand the material that is to be doped. Interfacial stress is formed at aninterface between two layers on account of the different latticeconstants and expansion coefficients of the two layer materials or, inthe case of amorphous materials, only as a result of the expansioncoefficients.

[0006] An example in which this problem leads to considerablerestrictions in the choice of material relates to trench capacitors inDRAM memory cells.

[0007] A memory cell of this type comprises a read-out transistor and astorage capacitor. The information is stored in the storage capacitor inthe form of an electric charge which represents a logic 0 or 1. Thisinformation can be read out via a bit line by driving the read-outtransistor via a word line. To reliably store the charge and, at thesame time, to allow differentiation of the information which is readout, the storage capacitor must have a minimum capacitance. The lowerlimit for the capacitance of the storage capacitor is currently regardedas being 25 fF.

[0008] Since the storage density increases from memory generation tomemory generation, the surface area required by the single-transistormemory cell has to be reduced from generation to generation. At the sametime, the minimum capacitance of the storage capacitor has to beretained.

[0009] Up to the 1 Mbit generation, both the read-out transistor and thestorage capacitor were produced as planar components. Beyond the 4 Mbitmemory generation, a further reduction in area of the memory cell wasachieved by means of a three-dimensional arrangement of read-outtransistor and storage capacitor. One possibility is for the storagecapacitor to be produced in a trench (cf. for example K. Yamada et al.,Proc. Intern. Electronic Devices and Materials IEDM 85, pp. 702 ff). Inthis case, a diffusion region which adjoins the wall of the trench and adoped polysilicon filling which is located in the trench act aselectrodes of the storage capacitor. The electrodes of the storagecapacitor are therefore arranged along the surface of the trench. Thisincreases the effective surface area of the storage capacitor, on whichthe capacitance is dependent, with respect to the space required for thestorage capacitor at the surface of the substrate, which corresponds tothe cross section of the trench. The packing density can be increasedfurther by reducing the cross section of the trench. However, there arelimits on the extent to which the depth of the trench can be increased,for technological reasons.

[0010] Currently, only a material that requires no appropriate stressmatching, in particular polysilicon, is selected for the trench filling.However, these materials alone have an excessively high impedance forfuture applications in trench capacitors.

[0011] Examples which may be mentioned of low-impedance materials forthe trench filling are metals, in particular metal silicides. A metalelectrode of this type can be used as an upper and/or as a bottomelectrode of the trench capacitor.

[0012] It has been proposed in a commonly assigned German patentapplication (DE 199 41 096.8, as yet unpublished), for the lower and/orupper capacitor electrode of a memory cell with select transistor andtrench capacitor to be designed as a metallic electrode. In that case,the upper capacitor electrode may also comprise two layers—tungstensilicide and polysilicon.

[0013] Furthermore, U.S. Pat. No. 5,905,279 describes a memory cellhaving a storage capacitor, which is arranged in a trench, and a selecttransistor, in which the storage capacitor has a lower capacitorelectrode, which adjoins a wall of the trench, a capacitor dielectricand an upper capacitor electrode, and the upper capacitor electrodecomprises a conductive layer, in particular comprising WSi, TiSi, W, Tior TiN.

[0014] However, a problem with the use of a metal electrode is theoccurrence of mechanical stresses both at the interface between metalelectrode and adjoining semiconductor layer and in the bulk. Thesestresses have to be minimized in order to construct an electrical devicewhich is able to function.

[0015] Furthermore, U.S. Pat. No. 6,180,480 describes a method for thefabrication of a trench capacitor in which the trench, which has a highaspect ratio, is filled with a SiGe filling, as a result of first of alla SiGe layer being deposited over the wafer surface, and then a heattreatment step being carried out at a suitable temperature, during whichstep the SiGe layer melts, so that the trench is filled completely,without voids, with the SiGe filling.

[0016] A further example in which interfacial and bulk stress whichoccurs may lead to limits being imposed on the performance of the deviceis the high doping of semiconductor materials, for example the highdoping of the silicon substrate during the fabrication of the lowercapacitor electrode of a trench capacitor. More specifically, the lowercapacitor electrode is currently formed by a highly doped (dopantconcentration approximately 10¹⁹ cm⁻³) silicon region. The high dopantconcentration is limited by the interfacial stress which occurs betweensilicon substrate and capacitor dielectric.

SUMMARY OF THE INVENTION

[0017] It is accordingly an object of the invention to provide astress-reduced layer system, an improved memory capacitor, and a memorycell, which overcomes the above-mentioned disadvantages of theheretofore-known devices and methods of this general type and whichprovides a layer system with at least one first layer of semiconductormaterial, conducting or insulating material, which adjoins a conductingor insulating second layer, in which the mechanical stresses at theinterface are reduced.

[0018] It is a particular object of the present invention to provide animproved storage capacitor and a memory cell having a storage capacitorof this type.

[0019] With the foregoing and other objects in view there is provided,in accordance with the invention, a storage capacitor, in particular acapacitor for a DRAM memory cell, comprising:

[0020] a lower capacitor electrode, a storage dielectric, and an uppercapacitor electrode;

[0021] at least one of said lower and upper capacitor electrodes being aconductive layer;

[0022] a doped layer of SiGe, SiC, or GaAs, or a doped filling of SiGe,SiC, or GaAs disposed between said conductive layer and said storagedielectric, or disposed on a side of said conductive layer that isremote from said storage dielectric; and

[0023] with the proviso that a doped SiGe layer is not disposed betweensaid storage dielectric and said upper capacitor electrode.

[0024] In other words, the object is achieved by a storage capacitor, inparticular for use in a DRAM memory cell, having a lower capacitorelectrode, a storage dielectric and an upper capacitor electrode, atleast one of the two capacitor electrodes being a conductive layer orfilling, and a doped SiGe, SiC or GaAs layer or a doped SiGe, SiC orGaAs filling being arranged between the conductive layer or filling andthe storage dielectric or on that side of the conductive layer which isremote from the storage dielectric, with the proviso that a doped SiGelayer is not arranged between the storage dielectric and the uppercapacitor electrode.

[0025] The object is also achieved by a storage capacitor, in particularfor use in a DRAM memory cell, having a lower capacitor electrode, astorage dielectric, and an upper capacitor electrode, the lowercapacitor electrode being a conductive layer, and a doped Si layer beingarranged between the conductive layer and the storage dielectric.

[0026] The present invention also provides a memory cell having astorage capacitor as defined above, which is designed as a trenchcapacitor, and a select transistor, which comprises a source electrode,a drain electrode, a gate electrode and a conductive channel, the uppercapacitor electrode being electrically conductively connected to thesource or drain electrode.

[0027] The present invention also provides a memory cell having astorage capacitor as defined above, which is designed as a stackedcapacitor, and a select transistor, which comprises a source electrode,a drain electrode, a gate electrode, and a conductive channel, the lowercapacitor electrode being applied to an electrically conductiveconnection structure and being electrically conductively connected tothe source or drain electrode via this connection structure.

[0028] In the storage capacitor defined above, at least one capacitorelectrode is a conductive layer or filling. It preferably containsmetal, i.e. may, for example, be selected from metal silicide, metalnitride, metal carbide, WN, WSiN, WC, TiN, TaN or TaSiN.

[0029] The result is a stress-reduced layer system having at least onefirst layer of polycrystalline or single-crystal semiconductor material,which adjoins a microcrystalline or amorphous conducting or insulatingsecond layer, the semiconductor layer being doped with at least twodopants of the same conductivity type, of which at least one is suitablefor reducing mechanical stresses at the interface.

[0030] Furthermore, the result is a stress-reduced layer system havingat least one first layer of semiconductor material, conducting orinsulating material and at least one conducting or insulating secondlayer, a further semiconductor layer, which is doped with at least onedopant which is suitable for reducing mechanical stresses at theinterface between the second layer and the first layer, being arrangedbetween the first layer and the second layer or being applied to theopposite surface of the first layer or second layer from the interface.

[0031] The present invention is substantially based on the discoverythat, as a result of the controlled introduction of impurities into asemiconductor layer, mechanical stresses at an interface betweensemiconductor layer and conducting or insulating layer or betweenconducting and insulating layer are reduced. The impurities have to beselected in such a manner that the mechanical properties are modified ina suitable way, while the electrical properties are retained in such amanner that a fully functional electrical component remains possible.

[0032] More precisely, impurities which produce a mechanicalprestressing of the polycrystalline or single-crystal layer areintroduced into the semiconductor layer. The impurities can beintroduced into the first semiconductor layer, which forms the interfacewith the second layer. However, it is also possible, optionally inaddition, for a further semiconductor layer, which is doped with asuitable impurity, to be applied. This semiconductor layer may then bearranged between the first and second layers or may be applied to theopposite surface of the first layer or the second layer from theinterface. This makes it possible for the interfacial and bulk stressesto be optimized substantially separately from one another.

[0033] By way of example, compressible mechanical stresses can beproduced in p-doped silicon by the doping with Al, Ga, In, Tl or by theuse of SiGe as transition layer with corresponding dopants, for exampleAl, Ga, In, Tl, B. By contrast, tensile mechanical stresses can beachieved by B-doping or by SiC with suitable dopants, for example Al,Ga, In, Tl, B. In this case, both the type of dopant and itsconcentration are of importance to the setting of the stress. In n-dopedsilicon, compressible mechanical stresses can be produced by the dopantsAs, Sb or by the use of a SiGe transition layer with correspondingdopants, for example As, Sb, P. Tensile mechanical stresses can beachieved by phosphorus doping of silicon or by SiC as transition layertogether with the corresponding dopants, in particular As, Sb and P.

[0034] Naturally, it is also possible for other impurities to be used asdopant, provided that they do not undesirably impair the electricalfunctionality.

[0035] The interfacial stress may in this case occur between asemiconductor layer, for example a polycrystalline or single-crystalsemiconductor material, in particular single-crystal or polycrystallinesilicon, and a single-crystal, microcrystalline or amorphous insulatinglayer. Insulating layers which can be used are in particular theamorphous materials Si₃N₄, SiO₂, SiON, Al₂O₃, Al₂O₃ together withadditions of Hf, Zr, Y and La, and the single-crystal materials Pr₂O₃,Nd₂O₃. However, the interfacial stress may also occur between asemiconductor layer as mentioned above and a microcrystalline oramorphous conducting layer, such as for example metal nitride, metalsilicide, metal carbide and in particular WN, WSiN, WC, TiN, TaN, TaSiN.

[0036] Materials which can be used for the further semiconductor layer,which is doped with a suitable dopant as mentioned above, are inparticular polycrystalline or single-crystal silicon, GaAs, SiGe andSiC.

[0037] If polycrystalline silicon is doped with a corresponding dopant,it is possible, in addition to the abovementioned possibilities forcrystalline silicon, in addition to select firstly suitable depositionconditions, such as for example temperature or pressure, and secondlysuitable subsequent heat treatments in order to adapt the stresses in asuitable way.

[0038] If a spatially varying doping profile is selected in one layer,the advantage ensues that it is possible both to adapt the stresses atthe interface and to reduce the stresses in the bulk.

[0039] The present invention may in particular be applied advantageouslyto trench capacitors or stacked capacitors for use in DRAM memory cells.

[0040] By way of example, it may be applied to a memory cell having astorage capacitor, which is designed as a trench capacitor, and a selecttransistor, which has source, drain and gate electrodes and a conductingchannel. The trench capacitor comprises a lower capacitor electrode, astorage dielectric and an upper capacitor electrode, which are arrangedat least partially in a trench. The upper capacitor electrode isconnected to the source or drain electrode of the select transistor. Thelower capacitor electrode may, for example, be formed by a highly dopedsemiconductor region, the stress which occurs between highly dopedsemiconductor region and storage dielectric being reduced by the factthat the semiconductor layer is doped with at least two dopants of thesame conductivity type, of which at least one is suitable for reducingmechanical stresses at the interface.

[0041] Alternatively, the lower capacitor electrode may be a conductivelayer, and a further semiconductor layer, which is doped with at leastone dopant which is suitable for reducing mechanical stresses at theinterface between the dielectric layer and the conductive layer, isarranged between the conductive layer and the dielectric layer or isapplied to the opposite surface of the conductive layer from theinterface. In particular, a suitably doped polysilicon layer may beprovided between the conductive layer and the dielectric layer.

[0042] The upper capacitor electrode may, for example, comprise acombination of a conductive layer, in particular a tungsten silicidelayer, and a suitably doped silicon-germanium filling. The stress whichoccurs between the storage dielectric and the conductive layer isreduced by the suitably doped SiGe filling. This design of the uppercapacitor electrode can be applied to a trench capacitor with anydesired form of the lower capacitor electrode.

[0043] However, the invention may also be applied to a memory cellhaving a storage capacitor, which is designed as a stacked capacitor,and a select transistor, which has source, drain and gate electrodes anda conductive channel. The stacked capacitor comprises a lower capacitorelectrode, which is applied to an electrically conductive connectionstructure and is connected to the source or drain electrode of theselect transistor via this connection structure, and a storagedielectric and an upper capacitor electrode. The lower capacitorelectrode may be formed from a conductive material, for example tungstensilicide, and the stress which occurs between storage dielectric andlower capacitor electrode is reduced by the fact that the electricallyconductive connection structure is formed from suitably dopedsilicon-germanium.

[0044] The present invention therefore provides the followingadvantages:

[0045] The stress between layers which are applied on top of one anotheris reduced. Consequently, layer detachment and/or the formation ofdefects, which in turn leads to the electrical properties of thecomponent being impaired, can be avoided.

[0046] The fact that there is a simple possibility of reducing thestress increases the choice of materials. For example, it is nowpossible to use low-impedance materials for capacitor electrodes, whichcould not have been used without stress matching.

[0047] Other features which are considered as characteristic for theinvention are set forth in the appended claims.

[0048] Although the invention is illustrated and described herein asembodied in a stress-reduced layer system, it is nevertheless notintended to be limited to the details shown, since various modificationsand structural changes may be made therein without departing from thespirit of the invention and within the scope and range of equivalents ofthe claims.

[0049] The construction and method of operation of the invention,however, together with additional objects and advantages thereof will bebest understood from the following description of specific embodimentswhen read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIGS. 1 to 4 are diagrammatic sectional side views illustratingthe steps involved in forming a memory cell, in which the lowercapacitor electrode comprises a stress-reduced layer system;

[0051]FIG. 5 is a plan view showing a layout in an 8F² cellarchitecture;

[0052]FIGS. 6 and 7 are side views illustrating the steps involved informing a memory cell in which the lower capacitor electrode likewisecomprises a stress-reduced layer system;

[0053] FIGS. 8 to 10 are side views illustrating the steps involved informing a memory cell in which the upper capacitor electrode comprises astress-reduced layer system;

[0054]FIG. 11 is a sectional side view showing a variant of the methodillustrated in FIGS. 8 to 10; and

[0055]FIG. 12 is a sectional side view of the structure of a memory cellwith stacked capacitor, in which the lower capacitor electrode comprisesa stress-reduced layer system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] Referring now to the figures of the drawing in detail and first,particularly, to FIGS. 1-4 thereof, there is described a first exemplaryembodiment, in which the stress reduction is achieved by doping thesemiconductor layer with at least two dopants of the same conductivitytype. Stress reduction of this type can advantageously be used whenforming the lower capacitor electrode of a trench capacitor, which isalso referred to as a bottom electrode.

[0057] Step 1: Preparation and Etching of the Capacitor Trenches

[0058] In FIG. 1, a silicon substrate 1 is shown with a main surface 2.A 5 nm thick SiO₂ layer 3 and a 200 nm thick Si₃N₄ layer 4 are appliedto the main surface 2. A non-illustrated 1000 nm thick BSG layer is thenapplied as hard mask material.

[0059] The BSG layer, the Si₃N₄ layer 4 and the SiO₂ layer 3 arepatterned in a plasma etching process using CF₄/CHF₃ and aphotolithographically produced mask, so that a hard mask is formed.After the photolithographically produced mask has been removed, trenches5 are etched into the main surface 1 in a further plasma etching processusing HBr/NF₃ and the hard mask as an etching mask. The BSG layer isthen removed by wet etching using H₂SO₄/HF.

[0060] The trenches 5 have a depth, for example, of 5 μm, a width of100×250 nm and are spaced apart by 100 nm.

[0061] Next, a 10 nm thick SiO₂ layer 6, which may also be doped, forexample by in-situ doping, is deposited. The deposited SiO₂ layer 6covers at least the walls of the trenches 5. By deposition of a 200 nmthick polysilicon layer, chemical mechanical polishing down to thesurface of the Si₃N₄ layer 4 and by etching back the polysilicon layerusing SF₆, a polysilicon filling 7 is produced in each of the trenches5, the surface of which filling is arranged 1000 nm below the mainsurface 2 (cf. FIG. 1). If appropriate, the chemical mechanicalpolishing may be dispensed with. The polysilicon filling 7 is used as asacrificial layer for the subsequent deposition of Si₃N₄ spacers. Then,the SiO₂ layer 6 is etched isotropically at the walls of the trenches 5.

[0062] Next, in a CVD process a 20 nm thick spacer layer 9, whichcomprises silicon nitride and/or silicon dioxide, is deposited and isetched in an anisotropic plasma etching process using CHF₃. The spacerlayer 9 which has just been deposited serves as a covering materialduring the step of selective formation of the metal silicide onuncovered silicon regions. In the finished memory cell, it serves todisconnect the parasitic transistor which would otherwise form at thislocation, and therefore acts as the insulation collar. Then, polysiliconis etched selectively with respect to Si₃N₄ and SiO₂, using SF₆. In theprocess, the polysilicon filling 7 is in each case completely removedfrom the trench 5. That part of the SiO₂ layer 6 which has now beenuncovered is removed by etching with NH₄F/HF (cf. FIG. 2). Then, ifappropriate, to widen the trenches 5 in their lower region, i.e. in theregion which is remote from the main surface 2, silicon is etchedselectively with respect to the spacer layer. This is achieved, forexample, by an isotropic etching step using ammonia, in which silicon isetched selectively with respect to Si₃N₄. The etching time is such that20 nm of silicon are etched. As a result, the cross section is widenedby 40 nm in the lower region of the trenches 5. As a result, thecapacitor area and therefore the capacitance of the capacitor can beconsiderably increased.

[0063] The drawings illustrate the process sequence with unwidenedtrenches.

[0064] Step 2: Formation of the Lower Capacitor Electrode

[0065] There then follows the doping of the silicon substrate with P andAs, with the result that an n⁺-doped region 11 is formed. According tothe present invention, an overall concentration of the dopants from 10²⁰to 10²¹ cm⁻³ is particularly advantageous. The ratio of P atoms to Asatoms is approximately 10:1 to 1:1.

[0066] The co-doping may take place by gas-phase doping using two gasesthat are admitted in succession and at different temperatures. The gascontaining the dopant with the lower diffusion constant, i.e. theAs-containing gas, is thereby admitted first. The gas containing thedopant with the greater diffusion constant, i.e. the P-containing gas,follows at a later stage.

[0067] However, it is also possible for a substrate which is doped, forexample, with phosphorus additionally to be doped with As, for exampleby deposition of an arsenic-doped silicate glass layer in a layerthickness of 50 nm and a TEOS-SiO₂ layer in a thickness of 20 nm,followed by a heat treatment step at 1000° C., 120 seconds, with theresult that a region 11 which is doped with arsenic and phosphorus isformed by outdiffusion from the arsenic-doped silicate glass into thephosphorus-doped silicon substrate 1.

[0068] Alternatively, the phosphorus-doped substrate may also, inaddition, be doped with arsenic by gas-phase doping, for example usingthe following parameters: 900° C., 399 Pa tributylarsine (TBA) [33percent], 12 min.

[0069] In the finished trench capacitor, the n⁺-doped region 11 acts asthe lower capacitor electrode. Furthermore, on account of its highdoping, the depletion zone is reduced in size, with the result that thecapacitance of the capacitor is further increased.

[0070] On account of the co-doping, it is possible for the n⁺-dopedregion 11 to be doped with a higher dopant concentration without stressforming as a result at the interface with the dielectric layer.Accordingly, the depletion zone can be made particularly small, with theresult that the capacitance of the capacitor becomes particularly great.

[0071] Step 3: Deposition of the Capacitor Dielectric

[0072] Next, a 5 nm thick dielectric layer 14, which contains SiO₂ andSi₃N₄ and also, if appropriate, silicon oxynitride, is deposited ascapacitor dielectric. This layer sequence can be produced by steps ofnitride deposition and of thermal oxidation, during which defects in thelayer below are annealed out. As an alternative, the dielectric layer 14contains Al₂O₃ (aluminum oxide), if appropriate with an addition of Hf,Zr, Y or La, or alternatively Pr₂O₃ or Nd₂O₃.

[0073] Step 4: Formation of the Upper Capacitor Electrode

[0074] Then, the upper capacitor electrode is formed. By way of example,a 200 nm thick in-situ doped polysilicon layer 15 is deposited, as shownin FIG. 3. The polysilicon layer 15 and the dielectric layer 14 areremoved down to the surface of the Si₃N₄ layer 4 by chemical mechanicalpolishing.

[0075] Step 5: Connection of the Upper Capacitor Electrode to the SelectTransistor

[0076] Next, the standard DRAM process is carried out, by means of whichthe upper capacitor electrode is suitably patterned and is connected tothe source/drain region of a select transistor.

[0077] This can be achieved, for example, by etching the polysiliconfilling 15 to approximately 100 nm below the main surface 2. This isfollowed by Si₃N₄ etching using HF/ethylene glycol, during which 10 nmof Si₃N₄ are etched, and etching using NH₄F/HF, by means of which SiO₂and dielectric material are etched. After sacrificial oxidation to forma non-illustrated screen oxide, an implantation step is carried out,during which an n⁺-doped region 16 is formed in the side wall of eachtrench 5 in the region of the main surface 2. As shown in FIG. 4, spacewhich remained free above the polysilicon filling 15 in the respectivetrench 5 is filled with a polysilicon filling 10 by deposition ofin-situ doped polysilicon and back-etching of the polysilicon using SF₆.In the finished storage capacitor, the polysilicon filling 15 acts asthe upper capacitor electrode. The polysilicon filling 10 acts as aconnection structure between the n⁺-doped region 16 and the polysiliconfilling 15 acting as the upper capacitor electrode.

[0078] Then, insulation structures 8 are produced, which surround theactive regions and thereby define these regions. For this purpose, amask which defines the active regions and is not shown, is formed. Theinsulation structures 8 are completed by nonselective plasma etching ofsilicon, SiO₂ and polysilicon with the aid of CHF₃/N₂/NF₃, the etchingtime being set in such a way that 200 nm of polysilicon are etched, byremoving the resist mask used by means of O₂/N₂, by wet-chemical etchingof 3 nm of dielectric layer, by oxidation and deposition of a 5 nm thickSi₃N₄ layer and by deposition of a 250 nm thick SiO₂ layer in a TEOSprocess and subsequent chemical mechanical polishing. Then, the Si₃N₄layer 4 is removed by etching in hot H₃PO₄, and the SiO₂ layer isremoved by etching in dilute hydrofluoric acid.

[0079] Next, a screen oxide is formed by sacrificial oxidation.Photolithographically produced masks and implantations are used to formn-doped wells, p-doped wells and to carry out threshold voltageimplantations in the region of the periphery and of the selecttransistors of the cell array. Furthermore, high-energy ion implantationis carried out for doping of the substrate region which is remote fromthe main surface 2. In this way, an n⁺-doped region, which connectsadjacent lower capacitor electrodes 13 to one another, is formed (knownas a buried-well implant).

[0080] Then, the transistor is completed by generally known methodsteps, by defining in each case the gate oxide and the gate electrodes18, corresponding interconnects and the source and drain electrodes 17.

[0081] Then, the memory cell is completed in a known way by formingfurther wiring levels.

[0082] The memory cell arrangement, the layout of which is illustratedfor an 8-F² cell architecture, by way of example, in FIG. 5, has foreach memory cell a storage capacitor arranged in one of the trenches 5and a planar select transistor. Each memory cell requires a space of8F², where F is the minimum feature size in the respective technology.The bit lines BL run in strip form and parallel to one another, thewidth of the bit line BL being in each case F, and the distance betweenthe bit lines likewise being F. The word lines WL, which likewise have awidth of F and are spaced apart by F, run perpendicular thereto. Belowthe bit lines BL there are active regions A, two word lines WL crossingabove each active region. The active regions A are in each case arrangedoffset with respect to one another below adjacent bit lines BL. A bitline contact BLK, which allows electrical connection between therespective bit line BL and the active region A, is arranged in thecenter of the active regions A. The trenches 5 are arranged below theword line WL. The gate electrode 26 of the associated select transistoris arranged in each case within the active regions at the crossing pointbetween one of the bit lines BL and one of the word lines WL.

[0083] The active regions A in each case extend between two trenches 5.They comprise two select transistors, which are connected to theassociated bit line BL via a common bit line contact BLK. Theinformation from the storage capacitor which is arranged in one or otherof the trenches 5 is read out depending on which of the word lines WL isdriven.

[0084] In a second exemplary embodiment, the lower capacitor electrodeis produced by a layer stack comprising tungsten silicide and dopedpolysilicon which is applied to the silicon substrate.

[0085] First of all, as described in the first exemplary embodimentunder step 1, the silicon substrate is prepared and the capacitortrenches are etched.

[0086] Step 2: Formation of the Lower Capacitor Electrode

[0087] First of all, if this has not already taken place by means of thedoped oxide, the silicon substrate is doped. This can be achieved, forexample, by deposition of an arsenic-doped silicate glass layer in alayer thickness of 50 nm and of a TEOS-SiO₂ layer in a thickness of 20nm, followed by a heat-treatment step at 1000° C., 120 seconds, with theresult that an n⁺-doped region 11 is formed by outdiffusion from thearsenic-doped silicate glass layer into the silicon substrate 1.Alternatively, gas-phase doping may also be carried out, for exampleusing the following parameters: 900° C., 399 Pa tributylarsine (TBA) [33percent], 12 min.

[0088] The goal of the n⁺-doped region 11 is to reduce the size of thedepletion zone, so that the capacitance of the capacitor is increasedfurther. Furthermore, the n⁺-doped region produces ohmic contact withthe metal electrode which is yet to be fabricated.

[0089] Then, the metal electrode 13, which in the present exemplaryembodiment consists of tungsten silicide, is applied. This can beachieved, for example, by deposition of tungsten silicide in the trenchor alternatively by selective formation of tungsten silicide on theuncovered silicon regions. The thickness of the metal electrode istypically about 10 to 30 nm.

[0090] Then, an approximately 10 to 30 nm thick polysilicon layer 19,which is doped with arsenic in a concentration of 10¹⁹ to 10²¹ cm⁻³, isapplied.

[0091] The role of the doped polysilicon interlayer 19 is to reduce theinterfacial stress between the tungsten silicide layer and thedielectric layer which is yet to be applied.

[0092] Then, the polysilicon interlayer 19 and, if appropriate, thetungsten silicide layer, if the latter has not been formed inself-aligned fashion on the uncovered silicon regions, are etched back.For this purpose, first of all a photoresist is introduced in the lowertrench region, the height of the resist filling being set by etchingusing N₂/O₂, and anisotropic etching is carried out using HCl/Cl₂/NF₃,during which step tungsten silicide is etched selectively with respectto Si₃N₄ and SiO₂ (cf. FIG. 6).

[0093] It is therefore possible, according to the present invention, forthe lower capacitor electrode to be designed as a metallic electrode,with the result that its conductivity is increased, and in addition forthe capacitance to be increased, on account of the reduction in the sizeof the depletion zone. At the same time, the polysilicon interlayer 19prevents adverse effects caused by stress between the lower capacitorelectrode and the capacitor dielectric.

[0094] The trench capacitor and then the memory cell are completed bycarrying out steps 3 to 5 which have been explained above in connectionwith the first exemplary embodiment (cf. FIG. 7).

[0095] According to a third exemplary embodiment of the presentinvention, the interfacial stress which occurs between an insulatinglayer and a conducting layer is reduced by means of a suitably dopedSiGe layer which is applied to the conductive layer. This canadvantageously be directed at the upper capacitor electrode of a trenchcapacitor.

[0096] Step 1 for preparation of the silicon substrate and for etchingof the capacitor trenches is carried out in the same way as that whichhas been described with reference to the first exemplary embodiment.

[0097] Step 2: Formation of the Lower Capacitor Electrode

[0098] If this has not already been achieved by the doped oxide, thesilicon substrate is doped. This can be achieved, for example, bydeposition of an arsenic-doped silicate glass layer in a layer thicknessof 50 nm and of a TEOS-SiO₂ layer in a thickness of 20 nm, followed by aheat treatment step at 1000° C., 120 seconds, with the result that ann⁺-doped region 11 is formed by outdiffusion from the arsenic-dopedsilicate glass layer into the silicon substrate 1. Alternatively,gas-phase doping may also be carried out, for example using thefollowing parameters: 900° C., 399 Pa tributylarsine (TBA) [33 percent],12 min.

[0099] The role of the n⁺-doped region is firstly to reduce the size ofthe depletion zone, with the result that the capacitance of thecapacitor is increased further. Secondly, the high dopant concentration,which is of the order of magnitude of 10¹⁹ cm⁻³, can provide the lowercapacitor electrode, if this is not metallic. If it is metallic, thehigh doping provides an ohmic contact.

[0100] Then, step 3 for deposition of the capacitor dielectric 14 iscarried out as described above (cf. FIG. 8).

[0101] Step 4: Formation of the Upper Capacitor Electrode

[0102] A tungsten silicide layer 20 is deposited by CVD. The space whichremains in the trenches 5 is filled with photoresist and etched backusing N₂/O₂. Tungsten silicide is then etched selectively with respectto Si₃N₄ and the dielectric layer 14 by anisotropic etching usingHCl/Cl₂/NF₃ in a plasma-enhanced etching process. An upper capacitorelectrode 15 comprising tungsten silicide is formed.

[0103] After the removal of the photoresist filling in an etchingprocess using O₂/N₂, remaining space in the trenches 5 is provided witha SiGe filling 21 by deposition of a 70 nm thick silicon-germanium layer21, which is doped with arsenic in a concentration of 10²⁰ to 10²¹ cm⁻³,and chemical mechanical polishing down to the surface of the Si₃N₄ layer4 (cf. FIG. 9). Silicon-germanium can be deposited by a CVD processusing silane or disilane and germane. The silicon-germanium layer has agermanium content of 10 to 50%.

[0104] Step 5: Connecting the Upper Capacitor Electrode to the SelectionTransistor

[0105] In a dry-etching step using SF₆ or HBr, the SiGe filling 21 isetched back 100 nm below the main surface 2. This is followed by anetching step using HF/ethylene glycol, which attacks the Si₃N₄ andnitride is etched. Uncovered parts of the dielectric layer 14 and of theSiO₂ layer 6 are removed with the aid of NH₄F/HF. After sacrificialoxidation to form a screen oxide (not shown), an implantation step iscarried out, during which an n⁺-doped region 16 is formed in the sidewall of each trench 5, in the region of the main surface 2. Space whichremains above the SiGe filling 21 in the respective trench 5 is filledwith a SiGe filling 12 by deposition of in-situ doped silicon-germaniumand back-etching of the silicon-germanium using SF₆ or HBr. In thefinished storage capacitor, the SiGe filling 21 acts as an uppercapacitor electrode. The silicon-germanium filling 12 acts as aconnection structure between the n⁺-doped region 16 and thesilicon-germanium filling 21, which acts as upper capacitor electrode.

[0106] Alternatively, it is also possible for a polysilicon filling tobe used instead of the silicon-germanium filling 12.

[0107] In a procedure in which the insulation collar is formed onlyafter the filling of the capacitor trench and the filling of thecapacitor trench takes place in a multistage process, it is alsopossible, for example, for those parts of the trench filling whichadjoin the insulation collar to be formed from polysilicon, while onlythe lower part of the trench filling is formed from silicon-germanium.

[0108] Then, insulation structures 8, which surround the active regionsand thereby define these regions, are produced. For this purpose, a maskwhich defines the active regions is formed (not shown). The insulationstructures 8 are completed by nonselective plasma etching of thesilicon, SiO₂ and silicon-germanium or polysilicon with the aid ofCHF₃/N₂/NF₃, with the etching time being set in such a way that 200 nmof silicon-germanium or polysilicon are etched, by removal of the resistmask used by means of O₂/N₂, by wet chemical etching of 3 nm ofdielectric layer, by oxidation and deposition of a 5 nm thick Si₃N₄layer and by deposition of a 250 nm thick SiO₂ layer using a TEOSprocess and subsequent chemical mechanical polishing. Then, the Si₃N₄layer 4 is removed by etching in hot H₃PO₄, and the SiO₂ layer 3 isremoved by etching in dilute hydrofluoric acid.

[0109] A screen oxide is then formed by sacrificial oxidation.Photolithographically produced masks and implantations are used to formn-doped wells, p-doped wells and to carry out threshold voltageimplantations in the region of the periphery and of the selecttransistors of the cell array. Furthermore, a high-energy ionimplantation is carried out in order to dope the substrate region whichis remote from the main surface 2.

[0110] In this way, an n⁺-doped region, which connects adjacent lowercapacitor electrodes to one another, is formed (known as a buried wellimplant).

[0111] Then, the transistor is completed by generally known methodsteps, by defining in each case the gate oxide and the gate electrodes18, corresponding interconnects and the source and drain electrode 17(cf. FIG. 10).

[0112] Then, the memory cell is completed in a known way by formingfurther wiring levels.

[0113] Alternatively, the upper capacitor electrode may also be producedin the manner illustrated in FIG. 11. For this purpose, first of all thetungsten silicide layer and then the silicon-germanium layer aredeposited in the capacitor trench.

[0114] The tungsten silicide layer 20, the silicon-germanium layer 21,the SiO₂ layer 6 and the dielectric layer 14 are etched back 100 nmbelow the main surface 2 by chemical mechanical polishing ofsilicon-germanium and tungsten silicide down to the surface of the Si₃N₄layer 4 and subsequent etching using HCl/Cl₂/NF₃, during which theetching rate of SiO₂ and silicon-germanium is higher than that oftungsten silicide. The result is an upper capacitor electrode 20, whichprojects above the height of the n⁺-doped region 11, and asilicon-germanium filling 21, which fills up the remaining space in thetrench 5 inside the upper capacitor electrode 20. This allows aparticularly low-impedance connection of the upper capacitor electrode20.

[0115] The structure of the upper capacitor electrode described in thethird embodiment, which comprises a tungsten silicide layer with a dopedSiGe filling, is advantageous compared to the known structure of anupper capacitor electrode comprising tungsten silicide layer with dopedpolysilicon filling, in that the solubility of the dopant in SiGe isgreater. As a result, a higher dopant concentration can be achieved inSiGe. This is advantageous firstly because, on account of a higherdoping capacity, improved stress matching of the interface betweendielectric and tungsten silicide layer can be achieved, and secondly,and also as a result, an increased doping capacity increases theconductivity. Moreover, the conductivity is additionally increased bythe fact that the mobility of the charge carriers is higher in SiGe.

[0116] The stress-reduced layer structure comprising dopedsilicon-germanium, a tungsten silicide layer and storage dielectric mayfurthermore also advantageously be used in a DRAM memory cell with astacked capacitor. In FIG. 12, reference numeral 31 denotes a siliconsubstrate, in which insulation trenches 33 are formed in order to definethe active regions, word lines and gate electrodes 35 and alsosource/drain regions 34. Contact structures 36 are provided in order toconnect the source/drain regions 34 to the lower electrode 37 of thestacked capacitors. The stacked capacitors also comprise a capacitordielectric 38 and an upper capacitor electrode 39. Bit line contacts 40for connection of the source/drain regions 34 to the bit line are alsoprovided.

[0117] In this case, the lower capacitor electrode 37 comprisingtungsten silicide is formed on a contact structure 36, which isfabricated from silicon-germanium. Doping the SiGe connection structurewith arsenic in a concentration of 10²⁰ to 10²¹ cm⁻³ advantageouslyminimizes the stress which would otherwise occur between the tungstensilicide layer and the storage dielectric. The silicon-germanium contactstructure has a germanium content of 10 to 50%.

We claim:
 1. A storage capacitor, comprising: a lower capacitorelectrode; a storage dielectric; and an upper capacitor electrode; atleast one of said lower and upper capacitor electrodes being aconductive layer; a doped layer selected from the group consisting of aSiGe layer, a SiC layer, and a GaAs layer or a doped filling selectedfrom the group consisting of a SiGe filling, a SiC filling, and a GaAsfilling disposed between said conductive layer and said storagedielectric; and wherein a doped SiGe layer is not disposed between saidstorage dielectric and said upper capacitor electrode.
 2. The storagecapacitor according to claim 1 configured to form a part of a DRAMmemory cell.
 3. The storage capacitor according to claim 1, wherein adopant for said SiGe layer is selected from the group consisting of Al,Ga, In, Tl, B, As, Sb, and P.
 4. The storage capacitor according toclaim 1, wherein a dopant for said SiC layer is selected from the groupconsisting of Al, Ga, In, Tl, B, As, Sb, and P.
 5. The storage capacitoraccording to claim 1, wherein said conductive layer is formed of amaterial selected from the group consisting of metal silicide, metalnitride, metal carbide, WN, WSiN, WC, TiN, TaN, and TaSiN.
 6. Thestorage capacitor according to claim 1, wherein said storage dielectriccontains a material selected from the group consisting of siliconnitride, silicon dioxide, silicon oxynitride, metal oxide, aluminumoxide, Pr₂O₃, Nd₂O₃, Al₂O₃ with an addition of Hf, Zr, Y or La.
 7. Thestorage capacitor according to claim 1, wherein said doped layer has adopant distribution with a gradient.
 8. A storage capacitor, comprising:a lower capacitor electrode; a storage dielectric; and an uppercapacitor electrode; at least one of said lower and upper capacitorelectrodes being a conductive layer; a doped layer selected from thegroup consisting of a SiGe layer, a SiC layer, and a GaAs layer or adoped filling selected from the group consisting of a SiGe filling, aSiC filling, and a GaAs filling disposed on a side of said conductivelayer remote from said storage dielectric; and wherein a doped SiGelayer is not disposed between said storage dielectric and said uppercapacitor electrode.
 9. The storage capacitor according to claim 8configured to form a part of a DRAM memory cell.
 10. The storagecapacitor according to claim 8, wherein a dopant for said SiGe layer isselected from the group consisting of Al, Ga, In, Tl, B, As, Sb, and P.11. The storage capacitor according to claim 8, wherein a dopant forsaid SiC layer is selected from the group consisting of Al, Ga, In, Tl,B, As, Sb, and P.
 12. The storage capacitor according to claim 8,wherein said conductive layer is formed of a material selected from thegroup consisting of metal silicide, metal nitride, metal carbide, WN,WSiN, WC, TiN, TaN, and TaSiN.
 13. The storage capacitor according toclaim 8, wherein said storage dielectric contains a material selectedfrom the group consisting of silicon nitride, silicon dioxide, siliconoxynitride, metal oxide, aluminum oxide, Pr₂O₃, Nd₂O₃, Al₂O₃ with anaddition of Hf, Zr, Y or La.
 14. The storage capacitor according toclaim 8, wherein said doped layer has a dopant distribution with agradient.
 15. A storage capacitor, comprising: a conductive layerforming a lower capacitor electrode; a storage dielectric; an uppercapacitor electrode; and a doped Si layer disposed between saidconductive layer and said storage dielectric.
 16. The storage capacitoraccording to claim 15 configured to form a part of a DRAM memory cell.17. The storage capacitor according to claim 15, wherein a dopant forsaid Si layer is selected from the group consisting of Al, Ga, In, Tl,B, As, Sb, and P.
 18. The storage capacitor according to claim 15,wherein said conductive layer is formed of a material selected from thegroup consisting of metal silicide, metal nitride, metal carbide, WN,WSiN, WC, TiN, TaN, and TaSiN.
 19. The storage capacitor according toclaim 15, wherein said storage dielectric contains a material selectedfrom the group consisting of silicon nitride, silicon dioxide, siliconoxynitride, metal oxide, aluminum oxide, Pr₂O₃, Nd₂O₃, Al₂O₃ with anaddition of Hf, Zr, Y or La.
 20. The storage capacitor according toclaim 15, wherein said Si layer contains a dopant introduced with agradient.
 21. A memory cell, comprising: a storage capacitor accordingto claim 1 formed as a trench capacitor with an upper capacitorelectrode; a selection transistor having a source electrode, a drainelectrode, a gate electrode, and a conductive channel; and wherein saidupper capacitor electrode is electrically connected to one of saidsource and drain electrodes.
 22. A memory cell, comprising: a storagecapacitor according to claim 8 formed as a trench capacitor with anupper capacitor electrode; a selection transistor having a sourceelectrode, a drain electrode, a gate electrode, and a conductivechannel; and wherein said upper capacitor electrode is electricallyconnected to one of said source and drain electrodes.
 23. A memory cell,comprising: a storage capacitor according to claim 15 formed as a trenchcapacitor with an upper capacitor electrode; a selection transistorhaving a source electrode, a drain electrode, a gate electrode, and aconductive channel; and wherein said upper capacitor electrode iselectrically connected to one of said source and drain electrodes.
 24. Amemory cell, comprising: a storage capacitor according to claim 1 formedas a stacked capacitor and having the lower capacitor electrode appliedon a connection structure; a selection transistor having a sourceelectrode, a drain electrode, a gate electrode, and a conductivechannel; and wherein said lower capacitor electrode is electricallyconductively connected to one of said source and drain electrodes viasaid connection structure.
 25. A memory cell, comprising: a storagecapacitor according to claim 8 formed as a stacked capacitor and havingthe lower capacitor electrode applied on a connection structure; aselection transistor having a source electrode, a drain electrode, agate electrode, and a conductive channel; and wherein said lowercapacitor electrode is electrically conductively connected to one ofsaid source and drain electrodes via said connection structure.
 26. Amemory cell, comprising: a storage capacitor according to claim 15formed as a stacked capacitor and having the lower capacitor electrodeapplied on a connection structure; a selection transistor having asource electrode, a drain electrode, a gate electrode, and a conductivechannel; and wherein said lower capacitor electrode is electricallyconductively connected to one of said source and drain electrodes viasaid connection structure.
 27. A storage capacitor, comprising: a lowercapacitor electrode; a storage dielectric; and an upper capacitorelectrode; at least one of said lower and upper capacitor electrodesbeing a conductive filling; a doped layer selected from the groupconsisting of a SiGe layer, a SiC layer, and a GaAs layer disposedbetween said conductive filling and said storage dielectric; and whereina doped SiGe layer is not disposed between said storage dielectric andsaid upper capacitor electrode.
 28. The storage capacitor according toclaim 27 configured to form a part of a DRAM memory cell.
 29. Thestorage capacitor according to claim 27, wherein a dopant for said SiGelayer is selected from the group consisting of Al, Ga, In, Tl, B, As,Sb, and P.
 30. The storage capacitor according to claim 27, wherein adopant for said SiC layer is selected from the group consisting of Al,Ga, In, Tl, B, As, Sb, and P.
 31. The storage capacitor according toclaim 27, wherein said conductive layer is formed of a material selectedfrom the group consisting of metal silicide, metal nitride, metalcarbide, WN, WSiN, WC, TiN, TaN, and TaSiN.
 32. The storage capacitoraccording to claim 27, wherein said storage dielectric contains amaterial selected from the group consisting of silicon nitride, silicondioxide, silicon oxynitride, metal oxide, aluminum oxide, Pr₂O₃, Nd₂O₃,Al₂O₃ with an addition of Hf, Zr, Y or La.
 33. The storage capacitoraccording to claim 27, wherein said doped layer has a dopantdistribution with a gradient.
 34. A memory cell, comprising: a storagecapacitor according to claim 27 formed as a trench capacitor with anupper capacitor electrode; a selection transistor having a sourceelectrode, a drain electrode, a gate electrode, and a conductivechannel; and wherein said upper capacitor electrode is electricallyconnected to one of said source and drain electrodes.
 35. A memory cell,comprising: a storage capacitor according to claim 27 formed as astacked capacitor and having the lower capacitor electrode applied on aconnection structure; a selection transistor having a source electrode,a drain electrode, a gate electrode, and a conductive channel; andwherein said lower capacitor electrode is electrically conductivelyconnected to one of said source and drain electrodes via said connectionstructure.